Circuits comprising or associated with a memory include the memory cell array that stores the data, memory periphery circuits that enable access to the memory cell array for READ and for WRITE, and external circuits. The memory cell array is generally arranged in rows and columns. Word lines that control access to the cells run in the row direction. Bit lines that carry data to and from the cell run in the column direction. The memory periphery circuits comprise row periphery that drives the word lines, column periphery that drives or senses the bit lines; address decode circuitry, and control circuitry. Generally, the row periphery includes means for disabling the word lines to avoid the possibility of data corruption during address transitions. The external circuits may interface with the memory but are not a direct part of the memory function and may comprise general logic and I/O buffers.
Power is supplied to a chip by a high voltage supply generally designated as Vdd, and a low voltage or reference supply generally designated as Vss. Chip power can be reduced by lowering or disconnecting from Vdd or raising or disconnecting from Vss. Some minimum voltage must be maintained for retention of volatile memory such as SRAM, and some minimum voltage must be maintained for logic operation.
Minimizing SRAM standby power during sleep/data retention mode is critical to many applications, especially in wireless devices and other portable devices. One prior art approach is to reduce the power supply voltage across the whole chip during sleep/data retention mode, such that the leakage current of the whole chip is reduced while the contents of the SRAM(s) on the chip are still retained. With the continued increment in the transistor leakage and the number of transistors on a chip, however, the total chip current leakage using this approach has become completely unacceptable for wireless applications based on state of art semiconductor technologies.
Another prior art approach that is being used for on-chip power management during sleep/data retention mode is to segment the voltage supply to allow different voltages to be supplied to a memory array versus to the memory periphery circuitry and other circuitry external to the memory. This is illustrated at 10 in FIG. 1. In the reduced power mode, the power supply voltage is reduced across selected SRAM array(s) whose contents need to be retained. Power is shut down to all other circuits (for example, by switches separating the circuitry from VDD and/or from VSS) except (a) the periphery circuitry associated with the selected SRAM array as required for integrity of the retained memory, (b) selected latches, flip-flops, etc. whose contents also need to be retained, and (c) sleep control circuits. Interface circuits are used when necessary along the boundary between different power domains to ensure that the selected SRAM array(s) and/or latches/flip-flops etc. maintain the data during the sleep/data retention mode and that no excessive through currents exist during the slow power down and up transitions. The periphery circuitry associated with the selected SRAM array(s) is powered to ensure that the word lines and bit lines of the selected SRAM array(s) are at determined voltage levels to prevent the contents of the SRAM cells from being corrupted. This is illustrated at 10 in FIG. 1, where the periphery power supplies are kept at the chip VDD/VSS levels, while either the array VDDA is lowered or the array VSSA is raised, or both methods are used to reduce the voltage across the array. In the power-down mode, the interface between the powered periphery circuitry and the external circuitry must be controlled such that the periphery is in a state that maintains the stored data.
The problem with the above approach is that the periphery leakage becomes significant as compared with the array leakage that is aggressively reduced by using much reduced voltages across the array and other advanced techniques, such as disclosed in the commonly assigned cross referenced patent application, the teaching of which is incorporated herein by reference. Even with the use of longer gate length or higher nwell bias, etc., the periphery current leakage cannot be reduced to significantly below the level of the array leakage in advanced CMOS technologies, since the direct gate tunneling leakage cannot be reduced.
Another prior art approach that is being used for on-chip power management during sleep/data retention mode is to shut down power to the memory periphery circuits. This approach requires the addition of circuitry to hold the memory in an unaccessed state while the periphery circuits are not powered. The problem with this approach is that the transition of control of the word lines between the periphery circuit word line drivers to the low power mode circuits is critical, and particularly difficult because of the relatively large word line drivers. Further, the circuitry required to hold each word line off may incur significant leakage.
Thus, there is a need for a low power mode with retained memory that has reduced power for the array and associated periphery and allows full removal of power to selected circuits, with low risk of corrupting the stored data and with low overhead.